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sprs106d ? october 1999 ? revised february 2003 1 post office box 1443 ? houston, texas 77251?1443 high-performance fixed-point digital signal processor (dsp) ? tms320c6205 ? 5-ns instruction cycle time ? 200-mhz clock rate ? eight 32-bit instructions/cycle ? 1600 mips velociti ? advanced-very-long-instruction- word (vliw) tms320c62x ? dsp core ? eight highly independent functional units: ? six alus (32-/40-bit) ? two 16-bit multipliers (32-bit result) ? load-store architecture with 32 32-bit general-purpose registers ? instruction packing reduces code size ? all instructions conditional instruction set features ? byte-addressable (8-, 16-, 32-bit data) ? 8-bit overflow protection ? saturation ? bit-field extract, set, clear ? bit-counting ? normalization 1m-bit on-chip sram ? 512k-bit internal program/cache (16k 32-bit instructions) ? 512k-bit dual-access internal data (64k bytes) ? organized as two 32k-byte blocks for improved concurrency 32-bit external memory interface (emif) ? glueless interface to synchronous memories: sdram or sbsram ? glueless interface to asynchronous memories: sram and eprom ? 52m-byte addressable external memory space four-channel bootloading direct-memory-access (dma) controller with an auxiliary channel flexible phase-locked-loop (pll) clock generator 32-bit/33-mhz peripheral component interconnect (pci) master/slave interface conforms to: pci specification 2.2 power management interface 1.1 meets requirements of pc99 ? pci access to all on-chip ram, peripherals, and external memory (via emif) ? four 8-deep x 32-wide fifos for efficient pci bus data transfer ? 3.3/5-v pci operation ? three pci bus address registers: prefetchable memory non-prefetchable memory i/o ? supports 4-wire serial eeprom interface ? pci interrupt request under dsp program control ? dsp interrupt via pci i/o cycle two multichannel buffered serial ports (mcbsps) ? direct interface to t1/e1, mvip, scsa framers ? st-bus-switching compatible ? up to 256 channels each ? ac97-compatible ? serial-peripheral-interface (spi) compatible (motorola ? ) two 32-bit general-purpose timers ieee-1149.1 (jtag ? ) boundary-scan-compatible 288-pin microstar bga ? package (ghk suffix) 0.15- m/5-level metal process ? cmos technology 3.3-v i/os, 1.5-v internal, 5-v voltage tolerance for pci i/o pins please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. velociti, tms320c62x, and microstar bga are trademarks of texas instruments. motorola is a trademark of motorola, inc. ? ieee standard 1149.1-1990 standard-test-access port and boundary scan architecture. copyright ? 2003, texas instruments incorporated
sprs106d ? october 1999 ? revised february 2003 2 post office box 1443 ? houston, texas 77251 ? 1443 table of contents electrical characteristics over recommended ranges of supply voltage and operating case temperature (pci only) 30 . . . . . . . . . . . . . . . . . . . . . . parameter measurement information 31 . . . . . . . . . . . . . . . input and output clocks 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing 34 . . . . . . . . . . . . . . . . . . . . . synchronous-burst memory timing 37 . . . . . . . . . . . . . . . . . synchronous dram timing 39 . . . . . . . . . . . . . . . . . . . . . . . . hold /holda timing 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing 46 . . . . . . . . . . . . . . . . . . . . . . . . . . pci i/o timings 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci reset timing 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci serial eeprom interface timing 49 . . . . . . . . . . . . . . . multichannel buffered serial port timing 50 . . . . . . . . . . . . . dmac, timer, power-down timing 60 . . . . . . . . . . . . . . . . . . jtag test-port timing 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . revision history 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ghk bga package (bottom view) 3 . . . . . . . . . . . . . . . . . . . description 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device characteristics 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional and cpu (dsp core) block diagram 6 . . . . . . . . . cpu (dsp core) description 7 . . . . . . . . . . . . . . . . . . . . . . . . memory map summary 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signal groups description 10 . . . . . . . . . . . . . . . . . . . . . . . . . . signal descriptions 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . documentation support 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock pll 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing 28 . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 29 . . . . . . . . . . . . . . . . . recommended operating conditions (pci only) 29 . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature 30 revision history this data sheet revision history highlights the technical changes made to the sprs106c device-specific data sheet to make it an sprs106d revision. scope: added further clarification to the clock pll and reset timing sections that initialization of the pll requires a falling edge of reset . page(s) no. additions/changes/deletions 26 clock pll section, figure 5. external pll circuitry for either pll multiply modes or x1 (bypass) mode: added note e, which states that the pll requires a falling edge of reset to initialize at power up. 44 reset timing, timing requirements for reset table: added further clarification to the ? pll requires a minimum value to stabilize following device power up ? footnote to include reference to the power up (specifically figure 5, note e) in the clock pll section.
sprs106d ? october 1999 ? revised february 2003 3 post office box 1443 ? houston, texas 77251 ? 1443 ghk bga package (bottom view) ghk 288-pin ball grid array (bga) package (bottom view) 7 j b a 1 d c e g f h 24 3 6 5 t k m l p n r w u v 12 8 9 10 11 15 14 13 16 17 18 19
sprs106d ? october 1999 ? revised february 2003 4 post office box 1443 ? houston, texas 77251 ? 1443 description the tms320c62x ? dsps (including the tms320c6205 device) compose the fixed-point dsp generation in the tms320c6000 ? dsp platform. the tms320c6205 (c6205) device is based on the high-performance, advanced velociti ? very-long-instruction-word (vliw) architecture developed by texas instruments (ti), making the c6205 an excellent choice for multichannel and multifunction applications. with performance of up to 1600 million instructions per second (mips) at a clock rate of 200 mhz, the c6205 offers cost-effective solutions to high-performance dsp-programming challenges. the c6205 dsp possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. this processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. the eight functional units provide six arithmetic logic units (alus) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. the c6205 can produce two multiply-accumulates (macs) per cycle for a total of 400 million macs per second (mmacs). the c6205 dsp also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. the c6205 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. program memory consists of a 64k-byte block that is user-configurable as cache or memory-mapped program space. data memory consists of two 32k-byte blocks of ram. the peripheral set includes two multichannel buffered serial ports (mcbsps), two general-purpose timers, a peripheral component interconnect (pci) module that supports 33-mhz master/slave interface and 4-wire serial eeprom interface, and a glueless external memory interface (emif) capable of interfacing to sdram or sbsram and asynchronous peripherals. the c6205 has a complete set of development tools which includes: a new c compiler, an assembly optimizer to simplify programming and scheduling, and a windows ? debugger interface for visibility into source code execution. tms320c6000 is a trademark of texas instruments. windows is a registered trademark of microsoft corporation.
sprs106d ? october 1999 ? revised february 2003 5 post office box 1443 ? houston, texas 77251 ? 1443 device characteristics table 1 provides an overview of the c6205 dsp. the table shows significant features of each device, including the capacity of on-chip ram, the peripherals, the execution time, and the package type with pin count, etc. table 1. characteristics of the c6205 processor hardware features c6205 emif 1 dma 4-channel with throughput enhancements peripherals pci 1 peri herals mcbsps 2 32-bit timers 2 internal program memory size (bytes) 64k internal program memory organization 1 block: 64k bytes cache/mapped program internal data memor size (bytes) 64k internal data memory organization 2 blocks: four 16-bit banks per block, 50/50 split cpu id+rev id control status register (csr.[31:16]) 0x0003 frequency mhz 200 cycle time ns 5 ns (c6205-200) core (v) 1.5 voltage i/o (v) 3.3 voltage voltage tolerance for pci i/o pins (v) 5.0 pll options clkin frequency multiplier bypass (x1), x4, x6, x7, x8, x9, x10, and x11 bga package 16 x 16 mm 288-pin microstar bga ? (ghk) process technology m 0.15 m product status product preview (pp) advance information (ai) production data (pd) pd device part numbers (for more details on the c6000 ? dsp part numbering, see figure 4) tmx320c6205ghk c6000 is a trademark of texas instruments.
sprs106d ? october 1999 ? revised february 2003 6 post office box 1443 ? houston, texas 77251 ? 1443 functional and cpu (dsp core) block diagram 32 32 control logic test c62x dsp core data path b b register file program access/cache controller instruction fetch instruction dispatch instruction decode data path a a register file data access controller power- down logic .l1 .s1 .m1 .d1 .d2 .m2 .s2 .l2 sdram or sbsram rom/flash sram i/o devices timer 0 timer 1 external memory interface (emif) multichannel buffered serial port 0 multichannel buffered serial port 1 direct memory access controller (dma) (4 channels) master/slave pci interface internal program memory 1 block program/cache (64k bytes) control registers internal data memory (64k bytes) 2 blocks of 4 banks each in-circuit emulation interrupt control framing chips: h.100, mvip, scsa, t1, e1 ac97 devices, spi devices, codecs c6205 digital signal processor pll (x1, x4, x6, x7, x8, x9, x10, x11) eeprom dma bus boot configuration interrupt selector peripheral control bus
sprs106d ? october 1999 ? revised february 2003 7 post office box 1443 ? houston, texas 77251 ? 1443 cpu (dsp core) description the cpu fetches velociti ? advanced very-long instruction words (vliw) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. the velociti ? vliw architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. the first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. fetch packets are always 256 bits wide; however, the execute packets can vary in size. the variable-length execute packets are a key memory-saving feature, distinguishing the c62x cpu from other vliw architectures. the cpu features two sets of functional units. each set contains four units and a register file. one set contains functional units .l1, .s1, .m1, and .d1; the other set contains units .d2, .m2, .s2, and .l2. the two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. the two sets of functional units, along with two register files, compose sides a and b of the cpu [see the functional and cpu (dsp core) block diagram and figure 1]. the four functional units on each side of the cpu can freely share the 16 registers belonging to that side. additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. while register access by functional units on the same side of the cpu as the register file can service all the units in a single clock cycle, register access using the register file across the cpu supports one read and one write per cycle. another key feature of the c62x cpu is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). two sets of data-addressing units (.d1 and .d2) are responsible for all data transfers between the register files and the memory. the data address driven by the .d units allows data addresses generated from one register file to be used to load or store data to or from the other register file. the c62x cpu supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. all instructions are conditional, and most can access any one of the 32 registers. some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically ? true ? ). the two .m functional units are dedicated for multiplies. the two .s and .l functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. the processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. the 32-bit instructions destined for the individual functional units are ? linked ? together by ? 1 ? bits in the least significant bit (lsb) position of the instructions. the instructions that are ? chained ? together for simultaneous execution (up to eight in total) compose an execute packet. a ? 0 ? in the lsb of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. if an execute packet crosses the 256-bit wide fetch-packet boundary, the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with nop instructions. the number of execute packets within a fetch packet can vary from one to eight. execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. after decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. while most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. all load and store instructions are byte-, half-word, or word-addressable.
sprs106d ? october 1999 ? revised february 2003 8 post office box 1443 ? houston, texas 77251 ? 1443 cpu (dsp core) description (continued) 8 8 2x 1x .l2 .s2 .m2 .d2 .d1 .m1 .s1 .l1 long src dst src 2 src 1 src 1 src 1 src 1 src 1 src 1 src 1 src 1 8 8 8 8 long dst long dst dst dst dst dst dst dst dst src 2 src 2 src 2 src 2 src 2 src 2 src 2 long src da1 da2 st1 ld1 ld2 st2 32 32 register file a (a0 ? a15) long src long dst long dst long src data path b data path a register file b (b0 ? b15) control register file figure 1. tms320c62x cpu (dsp core) data paths
sprs106d ? october 1999 ? revised february 2003 9 post office box 1443 ? houston, texas 77251 ? 1443 memory map summary table 2 shows the memory map address ranges of the c6205 device. the c6205 device has the capability of a map 0 or map 1 memory block configuration. the maps differ in that map 0 has external memory mapped at address 0x0000 0000 and map 1 has internal memory mapped at address 0x0000 0000. these memory block configurations are set up at reset by the boot configuration pins (generically called bootmode[4:0]). for the c6205 device, the bootmode configuration is handled, at reset, by the expansion bus module (specifically xd[4:0] pins). for more detailed information on the c6205 device settings, which include the device boot mode configuration at reset and other device-specific configurations, see the boot configuration section and the boot configuration summary table of the tms320c6000 peripherals reference guide (literature number spru190). table 2. tms320c6205 memory map summary memory block description block size hex address range map 0 map 1 block size (bytes) hex address range external memory interface (emif) ce0 internal program ram 64k 0000 0000 ? 0000 ffff emif ce0 reserved 4m ? 64k 0001 0000 ? 003f ffff emif ce0 emif ce0 12m 0040 0000 ? 00ff ffff emif ce1 emif ce0 4m 0100 0000 ? 013f ffff internal program ram emif ce1 64k 0140 0000 ? 0140 ffff reserved emif ce1 4m ? 64k 0141 0000 ? 017f ffff emif registers 256k 0180 0000 ? 0183 ffff dma controller registers 256k 0184 0000 ? 0187 ffff reserved 256k 0188 0000 ? 018b ffff mcbsp 0 registers 256k 018c 0000 ? 018f ffff mcbsp 1 registers 256k 0190 0000 ? 0193 ffff timer 0 registers 256k 0194 0000 ? 0197 ffff timer 1 registers 256k 0198 0000 ? 019b ffff interrupt selector registers 256k 019c 0000 ? 019f ffff reserved 256k 01a0 0000 ? 01a3 ffff pci registers 320k 01a4 0000 ? 01a8 ffff reserved 6m ? 576k 01a9 0000 ? 01ff ffff emif ce2 16m 0200 0000 ? 02ff ffff emif ce3 16m 0300 0000 ? 03ff ffff reserved 2g ? 64m 0400 0000 ? 7fff ffff internal data ram 64k 8000 0000 ? 8000 ffff reserved 2g ? 64k 8001 0000 ? ffff ffff
sprs106d ? october 1999 ? revised february 2003 10 post office box 1443 ? houston, texas 77251 ? 1443 signal groups description trst ext_int7 clock/pll ieee standard 1149.1 (jtag) emulation reserved reset and interrupts dma status power-down status control/status tdi tdo tms tck clkin clkmode0 pllv pllg pllf emu1 emu0 rsv2 rsv1 rsv0 nmi iack inum3 inum2 inum1 inum0 dmac3 dmac2 dmac1 dmac0 pd rsv4 rsv3 ext_int6 ext_int5 ext_int4 reset clkout2 rsv5 rsv7 rsv6 rsv8 rsv10 rsv9 rsv11 figure 2. cpu (dsp core) signals
sprs106d ? october 1999 ? revised february 2003 11 post office box 1443 ? houston, texas 77251 ? 1443 signal groups description (continued) ce3 are ed[31:0] ce2 ce1 ce0 ea[21:2] be3 be2 be1 be0 hold holda tout1 clkx1 fsx1 dx1 clkr1 fsr1 dr1 clks1 aoe awe ardy sda10 sdras /ssoe sdcas /ssads sdwe /sswe tout0 data memory map space select word address byte enables hold/ holda 32 20 asynchronous memory control synchronous memory control emif (external memory interface) timer 1 transmit timer 0 timers mcbsp1 receive clock mcbsps (multichannel buffered serial ports) tinp1 tinp0 clkx0 fsx0 dx0 clkr0 fsr0 dr0 clks0 transmit mcbsp0 receive clock figure 3. peripheral signals
sprs106d ? october 1999 ? revised february 2003 12 post office box 1443 ? houston, texas 77251 ? 1443 signal groups description (continued) ad[31:0] pcbe2 pcbe1 pcbe0 pgnt preq pclk pframe pinta data/address arbitration 32 clock control pci interface ppar prst pirdy pstop ptrdy pcbe3 pidsel pdevsel pperr pserr error command byte enable serial eeprom control xsp_do xsp_cs xsp_clk xsp_di power management pme 3.3vauxdet pwr_wkp 3.3vaux figure 3. peripheral signals (continued)
sprs106d ? october 1999 ? revised february 2003 13 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions signal type ? description name no. type ? description clock/pll clkin j3 i clock input clkout2 t19 o clock output at half of device speed ? used for synchronous memory interface clkmode0 l3 i clock mode select 0 ? selects whether the on-chip pll is used or bypassed. for more details, see the clock pll section. ? the pll multiply factor is selected at boot configuration. for more details, see the emif ? data pin descriptions and the clock pll section. pllv ? k5 a pll analog v cc connection for the low-pass filter pllg ? l2 a pll analog gnd connection for the low-pass filter pllf ? l1 a pll low-pass filter connection to external components and a bypass capacitor jtag emulation tms e17 i jtag test-port mode select (features an internal pullup) tdo d19 o/z jtag test-port data out tdi d18 i jtag test-port data in (features an internal pullup) tck d17 i jtag test-port clock trst c19 i jtag test-port reset (features an internal pulldown) emu1 e18 i/o/z emulation pin 1, pullup with a dedicated 20-k ? resistor ? emu0 f15 i/o/z emulation pin 0, pullup with a dedicated 20-k ? resistor ? reset and interrupts reset c3 i device reset nmi a8 i nonmaskable interrupt ? edge-driven (rising edge) ext_int7 b15 ext_int6 c15 i external interrupts ? edge driven ext_int5 a16 i ? edge-driven ? polarity inde p endently selected via the external interru p t polarity register bits (extpol.[3:0]) ext_int4 b16 ? polarity inde endently selected via the external interru t polarity register bits (extpol . [3:0]) iack a15 o interrupt acknowledge for all active interrupts serviced by the cpu inum3 f12 inum2 a14 o active interrupt identification number ? valid during iack for all active interrupts (not just external) inum1 b14 o ? valid during iack for all active interrupts (not just external) ? en cod in g o r de r f o ll o w s t h e in te rr u p t - se rvi ce f etc h-p ac k et o r de rin g inum0 c14 ? encoding order follows the interru t - service fetch - acket ordering power-down status pd b18 o power-down modes 2 or 3 (active if high) ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? pllv, pllg, and pllf are not part of external voltage supply or ground. see the clock pll section for information on how to connect these pins. a = analog signal (pll filter) ? for emulation and normal operation, pull up emu1 and emu0 with a dedicated 20-k ? resistor. for boundary scan, pull down emu1 and emu0 with a dedicated 20-k ? resistor.
sprs106d ? october 1999 ? revised february 2003 14 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal type ? description name no. type ? description pci interface pclk w5 i pci input clock ad31 d2 ad30 e3 ad29 e2 ad28 e1 ad27 f3 ad26 f5 ad25 f1 ad24 g3 ad23 h3 ad22 h2 ad21 j1 ad20 h1 ad19 m2 ad18 m1 ad17 n2 ad16 n1 i/o/z pci data address b s ad15 t1 i/o/z pci data-address bus ad14 v2 ad13 u2 ad12 u1 ad11 w3 ad10 w2 ad9 v1 ad8 u4 ad7 w4 ad6 u5 ad5 v5 ad4 u6 ad3 v6 ad2 v3 ad1 w6 ad0 u7 pcbe3 g2 pcbe2 m3 i/o/z pci command/b te enable signals pcbe1 t2 i/o/z pci command/byte enable signals pcbe0 v4 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs106d ? october 1999 ? revised february 2003 15 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal type ? description name no. type ? description pci interface (continued) pinta c1 o/z pci interrupt a preq f2 o/z pci bus request (bus arbitration) pserr p5 o/z pci system error pperr p2 i/o/z pci parity error prst c2 i pci reset pdevsel r2 i/o/z pci device select pgnt d1 i pci bus grant (bus arbitration) pframe n5 i/o/z pci frame pirdy p1 i/o/z pci initiator ready ppar t3 i/o/z pci parity pidsel h5 i pci initialization device select pstop r1 i/o/z pci stop ptrdy n3 i/o/z pci target ready xsp_clk c17 o serial eeprom clock xsp_di c18 i serial eeprom data in, pulldown with a dedicated 20-k ? resistor xsp_do b19 o serial eeprom data out xsp_cs c11 o serial eeprom chip select 3.3vauxdet b1 i 3.3-v auxiliary power supply detect. used to indicate the presence of 3.3vaux. a weak pulldown must be implemented to this pin. 3.3vaux b2 s 3.3-v auxiliary power supply voltage pme d3 o power management event pwr_wkp a2 i power wakeup signal emif ? control signals common to all types of memory ce3 v18 ce2 u17 o/z memory space enables ? enabled by bits 24 and 25 of the word address ce1 w18 o/z ? enabled by bits 24 and 25 of the word address ? only one asserted during any external data access ce0 v17 ? only one asserted during any external data access be3 u16 byte-enable control be2 w17 o/z b yte-ena bl e contro l ? decoded from the two lowest bits of the internal address be1 v16 o/z ? decoded from the two lowest bits of the internal address ? byte-write enables for most types of memory c b di tl t d t sdram d d it k i l (sdqm) be0 w16 yyy ? can be directly connected to sdram read and write mask signal (sdqm) emif ? address ea21 v7 ea20 w7 ea19 u8 o/z external address (word address) ea18 v8 o/z external address (word address) ea17 w8 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs106d ? october 1999 ? revised february 2003 16 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal type ? description name no. type ? description emif ? address (continued) ea16 w9 ea15 v9 ea14 u9 ea13 w10 ea12 v10 ea11 u10 ea10 w11 ea9 v11 o/z external address (word address) ea8 u11 o/z external address (word address) ea7 r11 ea6 w12 ea5 u12 ea4 r12 ea3 w13 ea2 v13 emif ? data ed31 f14 ed30 e19 ed29 f17 ed28 g15 ed27 f18 ed26 f19 ed25 g17 ed24 g18 external data ed23 g19 e x t erna l d a t a ? used for transfer of emif data ed22 h17 ? used for transfer of emif data ? also controls initialization of dsp modes at reset via pullup/pulldown resistors ed31 pll c f2 ed21 h18 ed31 - pll_conf2 ed27 - pll conf1 ed20 h19 i/o/z ed27 - pll _ conf1 ed23 - pll_conf0 ed19 j18 i/o/z ed23 pll _ conf0 ed15 - eeprom autoinitialization ed8 endianness ed18 j19 ed8 - endianness ed[7:5] - eeprom size ed17 k15 ed[7:5] - eeprom size ed[4:0] - bootmode ed16 k17 ed[4:0] bootmode ed15 k18 ed14 k19 ed13 l17 ed12 l18 ed11 l19 ed10 m19 ed9 m18 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs106d ? october 1999 ? revised february 2003 17 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal type ? description name no. type ? description emif ? data (continued) ed8 m17 ed7 n19 ed6 p19 ed5 n15 ed4 p18 i/o/z external data ed3 p17 i/o/z external data ed2 r19 ed1 r18 ed0 r17 emif ? asynchronous memory control are u14 o/z asynchronous memory read-enable aoe w14 o/z asynchronous memory output-enable awe v14 o/z asynchronous memory write-enable ardy w15 i asynchronous memory ready input emif ? synchronous dram (sdram)/synchronous burst sram (sbsram) control sda10 u19 o/z sdram address 10 (separate for deactivate command) sdcas /ssads v19 o/z sdram column-address strobe/sbsram address strobe sdras /ssoe u18 o/z sdram row-address strobe/sbsram output-enable sdwe /sswe t17 o/z sdram write-enable/sbsram write-enable emif ? bus arbitration hold p14 i hold request from the host holda v15 o hold-request-acknowledge to the host timer 0 tout0 e5 o timer 0 or general-purpose output tinp0 c5 i timer 0 or general-purpose input timer 1 tout1 a5 o timer 1 or general-purpose output tinp1 b5 i timer 1 or general-purpose input dma action complete status dmac3 a17 dmac2 b17 o dma action complete dmac1 c16 o dma action complete dmac0 a18 multichannel buffered serial port 0 (mcbsp0) clks0 a12 i external clock source (as opposed to internal) clkr0 b9 i/o/z receive clock clkx0 c9 i/o/z transmit clock dr0 a10 i receive data dx0 b10 o/z transmit data fsr0 e10 i/o/z receive frame sync fsx0 a9 i/o/z transmit frame sync ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs106d ? october 1999 ? revised february 2003 18 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal type ? description name no. type ? description multichannel buffered serial port 1 (mcbsp1) clks1 c6 i external clock source (as opposed to internal) clkr1 b6 i/o/z receive clock clkx1 e6 i/o/z transmit clock dr1 a7 i receive data dx1 b7 o/z transmit data fsr1 c7 i/o/z receive frame sync fsx1 a6 i/o/z transmit frame sync reserved for test rsv0 c8 i reserved for testing, pullup with a dedicated 20-k ? resistor rsv1 a4 i reserved for testing, pullup with a dedicated 20-k ? resistor rsv2 k3 i reserved for testing, pullup with a dedicated 20-k ? resistor rsv3 l5 o reserved (leave unconnected, do not connect to power or ground) rsv4 t18 o reserved (leave unconnected, do not connect to power or ground) rsv5 a3 o reserved (leave unconnected, do not connect to power or ground) rsv6 b3 o reserved (leave unconnected, do not connect to power or ground) rsv7 b4 o reserved (leave unconnected, do not connect to power or ground) rsv8 c4 o reserved (leave unconnected, do not connect to power or ground) rsv9 k2 o reserved (leave unconnected, do not connect to power or ground) rsv10 j17 o reserved (leave unconnected, do not connect to power or ground) rsv11 n18 o reserved (leave unconnected, do not connect to power or ground) supply voltage pins b8 e7 e8 e9 e11 e13 h14 k14 dv dd l15 s 3.3-v i/o supply voltage dv dd m14 s 3.3 v i/o su ly voltage p15 r8 r9 r10 r13 r14 u15 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs106d ? october 1999 ? revised february 2003 19 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal type ? description name no. type ? description supply voltage pins (continued) b12 e14 f9 f10 g5 h15 j2 cv j5 s 1 5 v core supply voltage cv dd j15 s 1.5-v core supply voltage m5 m15 n17 p6 p9 p12 u13 pci supply voltage pins g1 v iop p3 s 3.3/5-v pci clamp pins v iop u3 s 3.3/5 v pci clam ins f6 j6 v l6 s 3 3 v pci power supply pins v ddp r3 s 3.3-v pci power supply pins r6 r7 ground pins a11 a13 b11 b13 c10 v c12 gnd ground pins v ss c13 gnd ground pins e12 g7 g8 g9 g10 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs106d ? october 1999 ? revised february 2003 20 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal type ? description name no. type ? description ground pins (continued) g11 g12 g13 h7 h8 h9 h10 h11 h12 h13 j7 j8 j9 j10 j11 j12 j13 k1 k7 v ss k8 gnd ground pins v ss k9 gnd ground ins k10 k11 k12 k13 l7 l8 l9 l10 l11 l12 l13 m7 m8 m9 m10 m11 m12 m13 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs106d ? october 1999 ? revised february 2003 21 post office box 1443 ? houston, texas 77251 ? 1443 signal descriptions (continued) signal type ? description name no. type ? description ground pins (continued) n7 n8 n9 v n10 gnd gro nd pins v ss n11 gnd ground pins n12 n13 v12 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
sprs106d ? october 1999 ? revised february 2003 22 post office box 1443 ? houston, texas 77251 ? 1443 development support ti offers an extensive line of development tools for the tms320c6000 ? dsp platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the following products support development of c6000 ? dsp-based applications: software development tools: code composer studio ? integrated development environment (ide) including editor c/c++/assembly code generation, and debug plus additional development tools scalable, real-time foundation software (dsp bios), which provides the basic run-time target software needed to support any dsp application. hardware development tools: extended development system (xds ? ) emulator (supports c6000 ? dsp multiprocessor system debug) evm (evaluation module) the tms320 dsp development support reference guide (spru011) contains information about development-support products for all tms320 ? dsp family member devices, including documentation. see this document for further information on tms320 ? dsp documentation or any tms320 ? dsp support products from texas instruments. an additional document, the tms320 third-party support reference guide (spru052), contains information about tms320 ? dsp-related products from other companies in the industry. to receive tms320 ? dsp literature, contact the literature response center at 800/477-8924. for a complete listing of development-support tools for the tms320c6000 ? dsp platform, visit the texas instruments web site on the worldwide web at http://www.ti.com uniform resource locator (url) and select ? find development tools ? . for device-specific tools, under ? semiconductor products ? select ? digital signal processors ? , choose a product family, and select the particular dsp device. for information on pricing and availability, contact the nearest ti field sales office or authorized distributor. code composer studio, xds, and tms320 are trademarks of texas instruments.
sprs106d ? october 1999 ? revised february 2003 23 post office box 1443 ? houston, texas 77251 ? 1443 device and development-support tool nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all tms320 ? dsp devices and support tools. each tms320 ? dsp commercial family member has one of three prefixes: tmx, tmp, or tms. texas instruments recommends two of three possible prefix designators for support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmx/tmdx) through fully qualified production devices/tools (tms/tmds). device development evolutionary flow: tmx experimental device that is not necessarily representative of the final device ? s electrical specifications tmp final silicon die that conforms to the device ? s electrical specifications but has not completed quality and reliability verification tms fully qualified production device support tool development evolutionary flow: tmdx development-support product that has not yet completed t exas instruments internal qualification testing. tmds fully qualified development-support product tmx and tmp devices and tmdx development-support tools are shipped against the following disclaimer: ? developmental product is intended for internal evaluation purposes. ? tms devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti ? s standard warranty applies. predictions show that prototype devices (tmx or tmp) have a greater failure rate than the standard production devices. t exas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also incl udes a suffix with the device family name. this suffix indicates the package type (for example, ghk), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -200 is 200 mhz). figure 4 provides a legend for reading the complete device name for any tms320c6000 ? dsp family member. for the c6205 device orderable part numbers (p/ns), see the texas instruments web site on the worldwide web at http://www.ti.com url, or contact the nearest ti field sales office, or authorized distributor.
sprs106d ? october 1999 ? revised february 2003 24 post office box 1443 ? houston, texas 77251 ? 1443 device and development-support tool nomenclature (continued) prefix device speed range tms 320 c 6205 ghk 200 tmx = experimental device tmp = prototype device tms = qualified device smj = mil-prf-38535, qml sm = high rel (non-38535) device family 320 = tms320 dsp family technology package type ? gfn = 256-pin plastic bga ggp = 352-pin plastic bga gjc = 352-pin plastic bga gjl = 352-pin plastic bga gls = 384-pin plastic bga glw = 340-pin plastic bga ghk = 288-pin plastic microstar bga c = cmos device c6000 dsp: 6201 6204 6414 6711 6202 6205 6415 6712 6202b 6211 6416 6203 6211b 6701 ? bga = ball grid array temperature range (default: 0 c to 90 c) ( ) blank = 0 c to 90 c, commercial temperature a= ? 40 c to 105 c, extended temperature 100 mhz 120 mhz 150 mhz 167 mhz 200 mhz 233 mhz 250 mhz 300 mhz figure 4. tms320c6000 ? dsp platform device nomenclature (including the tms320c6205 device)
sprs106d ? october 1999 ? revised february 2003 25 post office box 1443 ? houston, texas 77251 ? 1443 documentation support extensive documentation supports all tms320 ? dsp family devices from product announcement through applications development. the types of documentation available include: data sheets, such as this document, with design specifications; complete user ? s reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. the following is a brief, descriptive list of support documentation specific to the c6000 ? dsp devices: the tms320c6000 cpu and instruction set reference guide (literature number spru189) describes the c6000 ? dsp core (cpu) architecture, instruction set, pipeline, and associated interrupts. the tms320c6000 peripherals reference guide (literature number spru190) describes the functionality of the peripherals available on the c6000 ? dsp platform of devices, such as the 64-/32-/16-bit external memory interfaces (emifs), 32-/16-bit host-port interfaces (hpis), multichannel buffered serial ports (mcbsps), direct memory access (dma), enhanced direct-memory-access (edma) controller, expansion bus (xb), peripheral component interconnect (pci), clocking and phase-locked loop (pll); and power-down modes. this guide also includes information on internal data and program memories. the tms320c6000 technical brief (literature number spru197) gives an introduction to the c62x ? /c67x ? devices, associated development tools, and third-party support. the tools support documentation is electronically available within the code composer studio ? integrated development environment (ide). for a complete listing of the latest c6000 ? dsp documentation, visit the texas instruments web site on the worldwide web at http://www.ti.com uniform resource locator (url). see the w orldwide web url for the new how to begin development with the tms320c6205 dsp application report (literature number spra596) which describes the functionalities unique to the c6205 device, especially the peripheral component interconnect (pci) module interface. c62x and c67x are trademarks of texas instruments.
sprs106d ? october 1999 ? revised february 2003 26 post office box 1443 ? houston, texas 77251 ? 1443 clock pll most of the internal c6205 clocks are generated from a single source through the clkin pin. this source clock either drives the pll, which multiplies the source clock in frequency to generate the internal cpu clock, or bypasses the pll to become the internal cpu clock. to use the pll to generate the cpu clock, the external pll filter circuit must be properly designed. figure 5, table 3, and table 4 show the external pll circuitry for either x1 (pll bypass) or x4 pll multiply modes. figure 6 shows the external pll circuitry for a system with only x1 (pll bypass) mode. to minimize the clock jitter, a single clean power supply should power both the c6205 device and the external clock oscillator circuit. noise coupling into pllf directly impacts pll clock jitter. the minimum clkin rise and fall times should also be observed. for the input clock timing requirements, see the input and output clocks electricals section. ed[31,27,23] (see table 3) pll pllv clkin loop filter pllclk pllmult clkin pllg c2 internal to c6205 cpu clock c1 r1 3.3v 10 f 0.1 f pllf emi filter c3 c4 1 0 clkmode0 (see table 3) notes: a. keep the lead length and the number of vias between pin pllf, pin pllg, r1, c1, and c2 to a minimum. in addition, place all pll components (r1, c1, c2, c3, c4, and emi filter) as close to the c6000 ? dsp device as possible. best performance is achieved with the pll components on a single side of the board without jumpers, switches, or components other than the ones shown. b. for reduced pll jitter, maximize the spacing between switching signals and the pll external components (r1, c1, c2, c3, c4, and the emi filter). c. the 3.3-v supply for the emi filter must be from the same 3.3-v power plane supplying the i/o voltage, dv dd . d. emi filter manufacturer: tdk part number acf451832-333, 223, 153, 103. panasonic part number exccet103u. e. at power up, the pll requires a falling edge of reset to initialize the pll engine. it may be necessary to toggle reset in order to establish proper pll operation. figure 5. external pll circuitry for either pll multiply modes or x1 (bypass) mode pll pllv clkin loop filter pllclk pllmult clkin pllg internal to c6205 cpu clock pllf 1 0 3.3v clkmode0 notes: a. for a system with only pll x1 (bypass) mode, short the pllf to pllg. b. the 3.3-v supply for pllv must be from the same 3.3-v power plane supplying the i/o voltage, dv dd . figure 6. external pll circuitry for x1 (bypass) pll mode only
sprs106d ? october 1999 ? revised february 2003 27 post office box 1443 ? houston, texas 77251 ? 1443 clock pll (continued) table 3. c6205 pll multiply modes and x1 (bypass) options clkmode0 ? ed[31] ? ed[27] ? ed[23] ? pll multiply factors cpu clock freq f(cpu clock) 0 x x x x1 (bypass) 1 x f (clkin) 1 0 0 0 x1 (bypass) 1 x f (clkin) 1 0 0 1 x4 4 x f (clkin) 1 0 1 0 x8 8 x f (clkin) 1 0 1 1 x10 10 x f (clkin) 1 1 0 0 x6 6 x f (clkin) 1 1 0 1 x9 9 x f (clkin) 1 1 1 0 x7 7 x f (clkin) 1 1 1 1 x11 11 x f (clkin) ? clkmode0 equal to 0 denotes on-chip pll bypassed clkmode0 equal to 1 denotes on-chip pll used, except when configuration bits (ed[31], ed[27], and ed[23]) are 0 at device reset. ? ed[31], ed[27], and ed[23] are the on-chip pll configuration bits that are latched during device reset, along with the other boot configuration bits ed[31:0]. table 4. c6205 pll component selection table clkmode clkin range (mhz) cpu clock frequency (clkout1) range (mhz) clkout2 range (mhz) r1 [ 1%] ( ? ) c1 [ 10%] (nf) c2 [ 10%] (pf) typical lock time ( s) x4 32.5 ? 50 x6 21.7 ? 33.3 x7 18.6 ? 28.6 x8 16.3 ? 25 130 ? 200 65 ? 100 60.4 27 560 75 x9 14.4 ? 22.2 130 200 65 100 60.4 27 560 75 x10 13 ? 20 x11 11.8 ? 18.2 under some operating conditions, the maximum pll lock time may vary as much as 150% from the specified typical value. for examp le, if the typical lock time is specified as 100 s, the maximum value may be as long as 250 s.
sprs106d ? october 1999 ? revised february 2003 28 post office box 1443 ? houston, texas 77251 ? 1443 power-supply sequencing ti dsps do not require specific power sequencing between the core supply and the i/o supply. however, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. system-level design considerations system-level design considerations, such as bus contention, may require supply sequencing to be implemented. in this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the i/o buffers. this is to ensure that the i/o buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board. power-supply design considerations for systems using the c6000 ? dsp platform of devices, the core supply may be required to provide in excess of 2 a per dsp until the i/o supply is powered up. this extra current condition is a result of uninitialized logic within the dsp(s) and is corrected once the cpu sees an internal clock pulse. with the pll enabled, as the i/o supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. with the pll disabled, as many as five external clock cycle pulses may be required to stop this extra current draw. a normal current state returns once the i/o power supply is turned on and the cpu sees a clock pulse. decreasing the amount of time between the core supply power up and the i/o supply power up can minimize the effects of this current draw. a dual-power supply with simultaneous sequencing, such as that available with tps563xx controllers or pt69xx plug-in power modules, can be used to eliminate the delay between core and i/o power up [see the using the tps56300 to power dsps application report (literature number slva088)]. a schottky diode can also be used to tie the core rail to the i/o rail, effectively pulling up the i/o power supply to a level that can help initialize the logic within the dsp. core and i/o supply voltage regulators should be located close to the dsp (or dsp array) to minimize inductance and resistance in the power delivery path. additionally, when designing for high-performance applications utilizing the c6000 ? platform of dsps, the pc board should include separate power planes for core, i/o, and ground, all bypassed with high-quality low-esl/esr capacitors.
sprs106d ? october 1999 ? revised february 2003 29 post office box 1443 ? houston, texas 77251 ? 1443 absolute maximum ratings over operating case temperature range (unless otherwise noted) ? supply voltage ranges: cv dd (see note 1) ? 0.3 v to 2.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dv dd (see note 1) ? 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (pci), v iop (see note 1) ? 0.5 v to 5.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (pci), v ddp (see note 1) ? 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage ranges: (except pci), v i ? 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (pci), v ip ? 0.5 v to v iop + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage ranges: (except pci), v o ? 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (pci), v op ? 0.5 v to v iop + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating case temperature range, t c 0 c to 90 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to v ss . recommended operating conditions min nom max unit cv dd supply voltage, core 1.43 1.5 1.57 v dv dd supply voltage, i/o 3.14 3.3 3.46 v v ss supply ground 0 0 0 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v i oh high-level output current ? 8 ma i ol low-level output current 8 ma t c operating case temperature 0 90 c recommended operating conditions (pci only) operation min nom max unit v ddp 3.3-v pci power supply voltage ? 3.3 v 3 3.3 3.6 v v 3 3/5 v pci clamp voltage (pci) 3.3 v 3 3.3 3.6 v v iop 3.3/5-v pci clamp voltage (pci) 5 v 4.75 5 5.25 v v inp t oltage (pci) 3.3 v ? 0.5 v iop + 0.5 v v ip input voltage (pci) 5 v ? 0.5 v iop + 0.5 v v high le el inp t oltage (pci) cmos compatible 3.3 v 0.5v iop v iop + 0.5 v v ihp high-level input voltage (pci) cmos-compatible 5 v 2 v iop + 0.5 v v lo le el inp t oltage (pci) cmos compatible 3.3 v ? 0.5 0.3v iop v v ilp low-level input voltage (pci) cmos-compatible 5 v ? 0.5 0.8 v ? the 3.3-v pci power supply voltage should follow similar sequencing as the i/o buffers supply voltage, see the power-supply seq uencing section of this data sheet.
sprs106d ? october 1999 ? revised february 2003 30 post office box 1443 ? houston, texas 77251 ? 1443 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage (except pci) dv dd = min, i oh = max 2.4 v v ol low-level output voltage (except pci) dv dd = min, i ol = max 0.6 v i i input current ? v i = v ss to dv dd 10 a i oz off-state output current v o = dv dd or 0 v 10 a i dd2v supply current, cpu + cpu memory access ? cv dd = nom, cpu clock = 200 mhz 290 ma i dd2v supply current, peripherals ? cv dd = nom, cpu clock = 200 mhz 240 ma i dd3v supply current, i/o pins ? dv dd = nom, cpu clock = 200 mhz 100 ma c i input capacitance 10 pf c o output capacitance 10 pf ? tms and tdi are not included due to internal pullups. trst is not included due to internal pulldown. ? measured with average activity (50% high/50% low power). for more details on cpu, peripheral, and i/o activity, see the tms320c6000 power consumption summary application report (literature number spra486). electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) (pci only) parameter pci side test conditions and operation min max unit v high le el o tp t oltage (pci) all pci pins i ohp = ? 0.5 ma 3.3 v 0.9v iop v v ohp high-level output voltage (pci) all pci pins i ohp = ? 2 ma 5 v 2.4 v v low level output voltage (pci) all pci pins i olp = 1.5 ma 3.3 v 0.1v iop v v olp low-level output voltage (pci) all pci pins i olp = 6 ma 5 v 0.55 v i lo le el inp t leakage c rrent (pci) all pci pins 0 < v ip < v iop 3.3 v 10 a i ilp low-level input leakage current (pci) all pci pins v ip = 0.5 v 5 v ? 70 a i ihp high-level input leakage current (pci) all pci pins v ip = 2.7 v 5 v 70 a input leakage currents include hi-z output leakage for all bidirectional buffers with 3-state outputs.
sprs106d ? october 1999 ? revised february 2003 31 post office box 1443 ? houston, texas 77251 ? 1443 parameter measurement information tester pin electronics v comm i ol c t i oh output under test 50 ? where: i ol = 2 ma i oh = 2 ma v comm = 0.8 v c t =15 ? 30-pf typical load-circuit capacitance figure 7. test load circuit for ac timing measurements signal transition levels all input and output timing parameters are referenced to 1.5 v for both ? 0 ? and ? 1 ? logic levels. v ref = 1.5 v figure 8. input and output voltage reference levels for ac timing measurements all rise and fall transition timing parameters are referenced to v il max and v ih min for input clocks, v ol max and v oh min for output clocks, v ilp max and v ihp min for pci input clocks, and v olp max and v ohp min for pci output clocks. v ref = v il max (or v ol max or v ref = v ih min (or v oh min or v ihp min or v ohp min) v ilp max or v olp max) figure 9. rise and fall transition time voltage reference levels
sprs106d ? october 1999 ? revised february 2003 32 post office box 1443 ? houston, texas 77251 ? 1443 input and output clocks timing requirements for clkin ?? (see figure 10) ? 200 no. pll mode x4, x6, x7, x8, x9, x10, x11 pll mode x1 unit min max min max 1 t c(clkin) cycle time, clkin 5 * m 5 ns 2 t w(clkinh) pulse duration, clkin high 0.4c 0.45c ns 3 t w(clkinl) pulse duration, clkin low 0.4c 0.45c ns 4 t t(clkin) transition time, clkin 5 0.6 ns ? the reference points for the rise and fall transitions are measured at v il max and v ih min. ? m = the pll multiplier factor (x4, x6, x7, x8, x9, x10, or x11). for more details, see the clock pll section of this data sheet . c = clkin cycle time in ns. for example, when clkin frequency is 50 mhz, use c = 20 ns. clkin 1 2 3 4 4 figure 10. clkin timings timing requirements for pclkin ? (see figure 11) no ? 200 unit no. min max unit 1 t c(pclk) cycle time, pclk 30 ns 2 t w(pclkh) pulse duration, pclk high 11 ns 3 t w(pclkl) pulse duration, pclk low 11 ns 4 t sr(pclk) ? v/ ? t slew rate, pclk 1 4 v/ns ? when the 5-v pci clamp is used, the reference points for the rise and fall transitions are measured v ilp max and v ihp min for 5 v operation. when the 3.3-v pci clamp is used, the reference points for the rise and fall transitions are measured at v ilp max and v ihp min for 3.3 v operation. pclk 1 2 3 4 4 2 v min peak to peak for 5v signaling or 0.4 v iop min peak to peak for 3v signaling figure 11. pclk timings
sprs106d ? october 1999 ? revised february 2003 33 post office box 1443 ? houston, texas 77251 ? 1443 input and output clocks (continued) switching characteristics over recommended operating conditions for clkout2 ?? (see figure 12) no parameter ? 200 unit no. parameter min max unit 1 t c(cko2) cycle time, clkout2 2p ? 0.7 2p + 0.7 ns 2 t w(cko2h) pulse duration, clkout2 high p ? 0.7 p + 0.7 ns 3 t w(cko2l) pulse duration, clkout2 low p ? 0.7 p + 0.7 ns 4 t t(cko2) transition time, clkout2 0.6 ns ? the reference points for the rise and fall transitions are measured at v ol max and v oh min. ? p = 1/cpu clock frequency in nanoseconds (ns). clkout2 1 2 3 4 4 figure 12. clkout2 timings
sprs106d ? october 1999 ? revised february 2003 34 post office box 1443 ? houston, texas 77251 ? 1443 asynchronous memory timing timing requirements for asynchronous memory cycles ??? (see figure 13 ? figure 16) no ? 200 unit no. min max unit 3 t su(edv-areh) setup time, edx valid before are high 1.5 ns 4 t h(areh-edv) hold time, edx valid after are high 3.5 ns 6 t su(ardyh-arel) setup time, ardy high before are low ? [(rst ? 3) * p ? 6] ns 7 t h(arel-ardyh) hold time, ardy high after are low (rst ? 3) * p + 3 ns 9 t su(ardyl-arel) setup time, ardy low before are low ? [(rst ? 3) * p ? 6] ns 10 t h(arel-ardyl) hold time, ardy low after are low (rst ? 3) * p + 3 ns 11 t w(ardyh) pulse width, ardy high 2p ns 15 t su(ardyh-awel) setup time, ardy high before awe low ? [(wst ? 3) * p ? 6] ns 16 t h(awel-ardyh) hold time, ardy high after awe low (wst ? 3) * p + 3 ns 18 t su(ardyl-awel) setup time, ardy low before awe low ? [(wst ? 3) * p ? 6] ns 19 t h(awel-ardyl) hold time, ardy low after awe low (wst ? 3) * p + 3 ns ? to ensure data setup time, simply program the strobe width wide enough. ardy is internally synchronized. if ardy does meet setu p or hold time, it may be recognized in the current cycle or the next cycle. thus, ardy can be an asynchronous input. ? rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold. these parameters are programmed via the emif ce space control registers. p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? the sum of rs and rst (or ws and wst) must be a minimum of 4 in order to use ardy input to extend strobe width. switching characteristics over recommended operating conditions for asynchronous memory cycles ?? # (see figure 13 ? figure 16) no parameter ? 200 unit no. parameter min typ max unit 1 t osu(selv-arel) output setup time, select signals valid to are low rs * p ? 2 ns 2 t oh(areh-seliv) output hold time, are high to select signals invalid rh * p ? 2 ns 5 t w(arel) pulse width, are low rst * p ns 8 t d(ardyh-areh) delay time, ardy high to are high 3p 4p + 5 ns 12 t osu(selv-awel) output setup time, select signals valid to awe low ws * p ? 2 ns 13 t oh(aweh-seliv) output hold time, awe high to select signals invalid wh * p ? 2 ns 14 t w(awel) pulse width, awe low wst * p ns 17 t d(ardyh-aweh) delay time, ardy high to awe high 3p 4p + 5 ns ? rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold. these parameters are programmed via the emif ce space control registers. p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? the sum of rs and rst (or ws and wst) must be a minimum of 4 in order to use ardy input to extend strobe width. # select signals include: cex , be[3:0] , ea[21:2], aoe; and for writes, include ed[31:0], with the exception that cex can stay active for an additional 7p ns following the end of the cycle.
sprs106d ? october 1999 ? revised february 2003 35 post office box 1443 ? houston, texas 77251 ? 1443 asynchronous memory timing (continued) setup = 2 strobe = 3 hold = 2 5 2 1 4 3 2 1 2 1 7 6 cpu clock ? cex be[3:0] ed[31:0] aoe are awe ardy 2 1 ea[21:2] ? cpu clock is an internal signal. figure 13. asynchronous memory read timing (ardy not used) setup = 2 strobe = 3 not ready hold = 2 8 2 1 4 3 2 1 2 1 2 1 11 10 9 cpu clock ? cex be[3:0] ed[31:0] aoe are awe ardy ea[21:2] ? cpu clock is an internal signal. figure 14. asynchronous memory read timing (ardy used)
sprs106d ? october 1999 ? revised february 2003 36 post office box 1443 ? houston, texas 77251 ? 1443 asynchronous memory timing (continued) setup = 2 strobe = 3 hold = 2 14 13 12 13 12 13 12 13 12 16 15 cpu clock ? cex be[3:0] ed[31:0] aoe are awe ardy ea[21:2] ? cpu clock is an internal signal. figure 15. asynchronous memory write timing (ardy not used) setup = 2 strobe = 3 not ready hold = 2 17 13 12 13 12 13 12 13 12 11 19 18 cpu clock ? cex be[3:0] ea[21:2] ed[31:0] aoe are awe ardy ? cpu clock is an internal signal. figure 16. asynchronous memory write timing (ardy used)
sprs106d ? october 1999 ? revised february 2003 37 post office box 1443 ? houston, texas 77251 ? 1443 synchronous-burst memory timing timing requirements for synchronous-burst sram cycles (see figure 17) no ? 200 unit no. min max unit 7 t su(edv-cko2h) setup time, read edx valid before clkout2 high 2.5 ns 8 t h(cko2h-edv) hold time, read edx valid after clkout2 high 1.5 ns switching characteristics over recommended operating conditions for synchronous-burst sram cycles ?? (see figure 17 and figure 18) no parameter ? 200 unit no. parameter min max unit 1 t osu(cev-cko2h) output setup time, cex valid before clkout2 high p ? 0.8 ns 2 t oh(cko2h-cev) output hold time, cex valid after clkout2 high p ? 4 ns 3 t osu(bev-cko2h) output setup time, bex valid before clkout2 high p ? 0.8 ns 4 t oh(cko2h-beiv) output hold time, bex invalid after clkout2 high p ? 4 ns 5 t osu(eav-cko2h) output setup time, eax valid before clkout2 high p ? 0.8 ns 6 t oh(cko2h-eaiv) output hold time, eax invalid after clkout2 high p ? 4 ns 9 t osu(adsv-cko2h) output setup time, sdcas /ssads valid before clkout2 high p ? 0.8 ns 10 t oh(cko2h-adsv) output hold time, sdcas /ssads valid after clkout2 high p ? 4 ns 11 t osu(oev-cko2h) output setup time, sdras /ssoe valid before clkout2 high p ? 0.8 ns 12 t oh(cko2h-oev) output hold time, sdras /ssoe valid after clkout2 high p ? 4 ns 13 t osu(edv-cko2h) output setup time, edx valid before clkout2 high p ? 1 ns 14 t oh(cko2h-ediv) output hold time, edx invalid after clkout2 high p ? 4 ns 15 t osu(wev-cko2h) output setup time, sdwe /sswe valid before clkout2 high p ? 0.8 ns 16 t oh(cko2h-wev) output hold time, sdwe /sswe valid after clkout2 high p ? 4 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as ssads , ssoe , and sswe , respectively, during sbsram accesses. for the first write in a series of one or more consecutive adjacent writes, the write data is generated one clkout2 cycle early to accommodate the ed enable time.
sprs106d ? october 1999 ? revised february 2003 38 post office box 1443 ? houston, texas 77251 ? 1443 synchronous-burst memory timing (continued) clkout2 cex be[3:0] ea[21:2] ed[31:0] sdcas /ssads ? sdras /ssoe ? sdwe /sswe ? be1 be2 be3 be4 a1 a2 a3 a4 q1 q2 q3 q4 12 11 10 9 6 5 4 3 2 1 8 7 ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as ssads , ssoe , and sswe , respectively, during sbsram accesses. figure 17. sbsram read timing clkout2 cex be[3:0] ea[21:2] ed[31:0] sdras /ssoe ? sdwe /sswe ? sdcas /ssads ? be1 be2 be3 be4 a1 a2 a3 a4 q1 q2 q3 q4 16 15 10 9 14 13 6 5 4 3 2 1 ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as ssads , ssoe , and sswe , respectively, during sbsram accesses. figure 18. sbsram write timing
sprs106d ? october 1999 ? revised february 2003 39 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing timing requirements for synchronous dram cycles (see figure 19) no ? 200 unit no. min max unit 7 t su(edv-cko2h) setup time, read edx valid before clkout2 high 1.25 ns 8 t h(cko2h-edv) hold time, read edx valid after clkout2 high 3 ns switching characteristics over recommended operating conditions for synchronous dram cycles ?? (see figure 19 ? figure 24) no parameter ? 200 unit no. parameter min max unit 1 t osu(cev-cko2h) output setup time, cex valid before clkout2 high p ? 1 ns 2 t oh(cko2h-cev) output hold time, cex valid after clkout2 high p ? 3.5 ns 3 t osu(bev-cko2h) output setup time, bex valid before clkout2 high p ? 1 ns 4 t oh(cko2h-beiv) output hold time, bex invalid after clkout2 high p ? 3.5 ns 5 t osu(eav-cko2h) output setup time, eax valid before clkout2 high p ? 1 ns 6 t oh(cko2h-eaiv) output hold time, eax invalid after clkout2 high p ? 3.5 ns 9 t osu(casv-cko2h) output setup time, sdcas /ssads valid before clkout2 high p ? 1 ns 10 t oh(cko2h-casv) output hold time, sdcas /ssads valid after clkout2 high p ? 3.5 ns 11 t osu(edv-cko2h) output setup time, edx valid before clkout2 high p ? 3 ns 12 t oh(cko2h-ediv) output hold time, edx invalid after clkout2 high p ? 3.5 ns 13 t osu(wev-cko2h) output setup time, sdwe /sswe valid before clkout2 high p ? 1 ns 14 t oh(cko2h-wev) output hold time, sdwe /sswe valid after clkout2 high p ? 3.5 ns 15 t osu(sda10v-cko2h) output setup time, sda10 valid before clkout2 high p ? 1 ns 16 t oh(cko2h-sda10iv) output hold time, sda10 invalid after clkout2 high p ? 3.5 ns 17 t osu(rasv-cko2h) output setup time, sdras /ssoe valid before clkout2 high p ? 1 ns 18 t oh(cko2h-rasv) output hold time, sdras /ssoe valid after clkout2 high p ? 3.5 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. for the first write in a series of one or more consecutive adjacent writes, the write data is generated one clkout2 cycle early to accommodate the ed enable time.
sprs106d ? october 1999 ? revised february 2003 40 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing (continued) clkout2 cex be[3:0] ea[15:2] ed[31:0] sda10 sdras /ssoe ? sdcas /ssads ? sdwe /sswe ? be1 be2 be3 ca1 ca2 ca3 d1 d2 d3 10 9 16 15 6 5 4 3 2 1 8 7 read read read ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. figure 19. three sdram read commands clkout2 cex be[3:0] ea[15:2] ed[31:0] sda10 sdras /ssoe ? sdcas /ssads ? sdwe /sswe ? be1 be2 be3 ca1 ca2 ca3 d1 d2 d3 14 13 10 9 16 15 12 11 6 5 4 3 2 1 write write write ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. figure 20. three sdram wrt commands
sprs106d ? october 1999 ? revised february 2003 41 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing (continued) clkout2 cex be[3:0] ea[15:2] ed[31:0] sda10 sdras /ssoe ? sdcas /ssads ? sdwe /sswe ? bank activate/row address row address 18 17 15 5 2 1 actv ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. figure 21. sdram actv command clkout2 cex be[3:0] ea[15:2] ed[31:0] sda10 sdras /ssoe ? sdcas /ssads ? sdwe /sswe ? 14 18 16 2 15 1 17 13 dcab ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. figure 22. sdram dcab command
sprs106d ? october 1999 ? revised february 2003 42 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing (continued) clkout2 cex be[3:0] ea[15:2] ed[31:0] sda10 sdras /ssoe ? sdcas /ssads ? sdwe /sswe ? 10 9 18 17 2 1 refr ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. figure 23. sdram refr command clkout2 cex be[3:0] ea[15:2] ed[31:0] sda10 sdras /ssoe ? sdcas /ssads ? sdwe /sswe ? mrs value 14 10 18 6 2 1 5 17 9 13 mrs ? sdcas /ssads , sdras /ssoe , and sdwe /sswe operate as sdcas , sdras , and sdwe , respectively, during sdram accesses. figure 24. sdram mrs command
sprs106d ? october 1999 ? revised february 2003 43 post office box 1443 ? houston, texas 77251 ? 1443 hold /holda timing timing requirements for the hold /holda cycles ? (see figure 25) no ? 200 unit no. min max unit 3 t oh(holdal-holdl) output hold time, hold low after holda low p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. switching characteristics over recommended operating conditions for the hold /holda cycles ?? (see figure 25) no parameter ? 200 unit no. parameter min max unit 1 t d(holdl-emhz) delay time, hold low to emif bus high impedance 4p ns 2 t d(emhz-holdal) delay time, emif bus high impedance to holda low 0 2p ns 4 t d(holdh-emlz) delay time, hold high to emif bus low impedance 3p 7p ns 5 t d(emlz-holdah) delay time, emif bus low impedance to holda high 0 2p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? emif bus consists of ce[3:0] , be[3:0] , ed[31:0], ea[21:2], are , aoe , awe , sdcas /ssads , sdras /ssoe , sdwe /sswe , and sda10. all pending emif transactions are allowed to complete before holda is asserted. the worst case for this is an asynchronous read or write with external ardy used or a minimum of eight consecutive sdram reads or writes when rbtr8 = 1. if no bus transactions are occurring , then the minimum delay time can be achieved. also, bus hold can be indefinitely delayed by setting nohold = 1. hold holda emif bus ? dsp owns bus external requestor owns bus dsp owns bus c6205 c6205 1 3 25 4 ? emif bus consists of ce[3:0] , be[3:0] , ed[31:0], ea[21:2], are , aoe , awe , sdcas /ssads , sdras /ssoe , sdwe /sswe , and sda10. figure 25. hold /holda timing
sprs106d ? october 1999 ? revised february 2003 44 post office box 1443 ? houston, texas 77251 ? 1443 reset timing timing requirements for reset (see figure 26) no ? 200 unit no. min max unit 1 t width of the reset pulse (pll stable) ? 10p ? ns 1 t w(rst) width of the reset pulse (pll needs to sync up) 250 s 10 t su(ed) setup time, ed boot configuration bits valid before reset high ? 5p ? # ns 11 t h(ed) hold time, ed boot configuration bits valid after reset high ? 5p ? ns ? this parameter applies to clkmode x1 when clkin is stable, and applies to clkmode x4, x6, x7, x8, x9, x10, and x11 when clkin and p ll are stable. ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. this parameter applies to clkmode x4, x6, x7, x8, x9, x10, and x11 only. the reset signal is not connected internally to the clock pll circuit. the pll requires a minimum of 250 s to stabilize following device power up or after pll configuration has been changed. during that time, reset must be asserted to ensure proper device operation. see the clock pll section for power up (specifically figure 5, note e) and for pll lock times (table 4). ? ed[31:0] are the boot configuration pins during device reset. # a 250 s setup time before the rising edge of reset is required when using clkmode x4, x6, x7, x8, x9, x10, or x11. switching characteristics over recommended operating conditions during reset ? || (see figure 26) no parameter ? 200 unit no. parameter min max unit 2 t d(rstl-cko2iv) delay time, reset low to clkout2 invalid p ns 3 t d(rsth-cko2v) delay time, reset high to clkout2 valid 4p ns 4 t d(rstl-highiv) delay time, reset low to high group invalid p ns 5 t d(rsth-highv) delay time, reset high to high group valid 4p ns 6 t d(rstl-lowiv) delay time, reset low to low group invalid p ns 7 t d(rsth-lowv) delay time, reset high to low group valid 4p ns 8 t d(rstl-zhz) delay time, reset low to z group high impedance p ns 9 t d(rsth-zv) delay time, reset high to z group valid 4p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. || high group consists of: holda low group consists of: iack, inum[3:0], dmac[3:0], pd, tout0, and tout1, xsp_clk, xsp_do, and xsp_cs z group consists of: ea[21:2], ed[31:0], ce[3:0] , be[3:0] , are , awe , aoe , sdcas /ssads , sdras /ssoe , sdwe /sswe , sda10, clkx0, clkx1, fsx0, fsx1, dx0, dx1, clkr0, clkr1, fsr0, fsr1, ad[31:0], pcbe[3:0] , pinta , preq , pserr , pperr , pdevsel , pframe , pirdy , ppar, pstop , ptrdy , and pme
sprs106d ? october 1999 ? revised february 2003 45 post office box 1443 ? houston, texas 77251 ? 1443 reset timing (continued) 9 8 7 6 5 4 3 2 11 10 reset clkout2 high group ? low group ? z group ? ed[31:0] ? 1 boot configuration ? high group consists of: holda low group consists of: iack, inum[3:0], dmac[3:0], pd, tout0, and tout1, xsp_clk, xsp_do, and xsp_cs z group consists of: ea[21:2], ed[31:0], ce[3:0] , be[3:0] , are , awe , aoe , sdcas /ssads , sdras /ssoe , sdwe /sswe , sda10, clkx0, clkx1, fsx0, fsx1, dx0, dx1, clkr0, clkr1, fsr0, fsr1, ad[31:0], pcbe[3:0] , pinta , preq , pserr , pperr , pdevsel , pframe , pirdy , ppar, pstop , ptrdy , and pme ? ed[31:0] are the boot configuration pins during device reset. figure 26. reset timing
sprs106d ? october 1999 ? revised february 2003 46 post office box 1443 ? houston, texas 77251 ? 1443 external interrupt timing timing requirements for interrupt response cycles ? (see figure 27) no ? 200 unit no. min max unit 2 t w(ilow) width of the interrupt pulse low 2p ns 3 t w(ihigh) width of the interrupt pulse high 2p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. switching characteristics over recommended operating conditions during interrupt response cycles ? (see figure 27) no parameter ? 200 unit no. parameter min max unit 1 t r(einth ? iackh) response time, ext_intx high to iack high 9p ns 4 t d(cko2l-iackv) delay time, clkout2 low to iack valid 0 10 ns 5 t d(cko2l-inumv) delay time, clkout2 low to inumx valid 0 10 ns 6 t d(cko2l-inumiv) delay time, clkout2 low to inumx invalid 0 10 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. interrupt number 6 5 4 4 3 2 clkout2 ext_intx, nmi 1 intr flag iack inumx figure 27. interrupt timing
sprs106d ? october 1999 ? revised february 2003 47 post office box 1443 ? houston, texas 77251 ? 1443 pci i/o timings timing requirements for pci inputs (see figure 28) no ? 200 unit no. min max unit 5 t su(iv-pclkh) setup time, input valid before pclk high 7 ns 6 t h(iv-pclkh) hold time, input valid after pclk high 0 ns switching characteristics over recommended operating conditions for pci outputs (see figure 28) no parameter ? 200 unit no. parameter min max unit 1 t d(pclkh-ov) delay time, pclk high to output valid 11 ns 2 t d(pclkh-oiv) delay time, pclk high to output invalid 2 ns 3 t d(pclkh-olz) delay time, pclk high to output low impedance 2 ns 4 t d(pclkh-ohz) delay time, pclk high to output high impedance 28 ns valid pclk 5 pci output pci input 3 valid 2 6 1 4 figure 28. pci intput/output timings
sprs106d ? october 1999 ? revised february 2003 48 post office box 1443 ? houston, texas 77251 ? 1443 pci reset timing timing requirements for pci reset (see figure 29) no ? 200 unit no. min max unit 1 t w(prst) pulse duration, prst 1 ms 2 t su(pclka-prsth) setup time, pclk active before prst high 100 s prst pclk 2 1 figure 29. pci reset (prst ) timings
sprs106d ? october 1999 ? revised february 2003 49 post office box 1443 ? houston, texas 77251 ? 1443 pci serial eeprom interface timing timing requirements for serial eeprom interface (see figure 30) no ? 200 unit no. min max unit 8 t su(div-clkh) setup time, xsp_di valid before xsp_clk high 50 ns 9 t h(clkh-div) hold time, xsp_di valid after xsp_clk high 0 ns switching characteristics over recommended operating conditions for serial eeprom interface ? (see figure 30) no parameter ? 200 unit no. parameter min nom max unit 1 t w(csl) pulse duration, xsp_cs low 2046p ns 2 t d(clkl-csl) delay time, xsp_clk low to xsp_cs low 0 ns 3 t d(csh-clkh) delay time, xsp_cs high to xsp_clk high 1023p ns 4 t w(clkh) pulse duration, xsp_clk high 1023p ns 5 t w(clkl) pulse duration, xsp_clk low 1023p ns 6 t osu(dov-clkh) output setup time, xsp_do valid after xsp_clk high 1023p ns 7 t oh(clkh-dov) output hold time, xsp_do valid after xsp_clk high 1023p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. 9 8 7 6 3 2 5 4 1 xsp_cs xsp_clk xsp_do xsp_di figure 30. pci serial eeprom interface timing
sprs106d ? october 1999 ? revised february 2003 50 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing timing requirements for mcbsp ?? (see figure 31) no ? 200 unit no. min max unit 2 t c(ckrx) cycle time, clkr/x clkr/x ext 2p ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x ext p ? 1 ? ns 5 t set p time e ternal fsr high before clkr lo clkr int 9 ns 5 t su(frh-ckrl) setup time, external fsr high before clkr low clkr ext 2 ns 6 t hold time e ternal fsr high after clkr lo clkr int 6 ns 6 t h(ckrl-frh) hold time, external fsr high after clkr low clkr ext 3 ns 7 t set p time dr alid before clkr lo clkr int 8 ns 7 t su(drv-ckrl) setup time, dr valid before clkr low clkr ext 0.5 ns 8 t hold time dr alid after clkr lo clkr int 4 ns 8 t h(ckrl-drv) hold time, dr valid after clkr low clkr ext 3 ns 10 t setup time external fsx high before clkx low clkx int 9 ns 10 t su(fxh-ckxl) setup time, external fsx high before clkx low clkx ext 2 ns 11 t hold time e ternal fsx high after clkx lo clkx int 6 ns 11 t h(ckxl-fxh) hold time, external fsx high after clkx low clkx ext 3 ns ? clkrp = clkxp = fsrp = fsxp = 0. if the polarity of any of the signals is inverted, then the timing references of that signal a re also inverted. ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. the maximum bit rate for the c6205 devices is 100 mbps or cpu/2 (the slower of the two). care must be taken to ensure that the ac timings specified in this data sheet are met. the maximum bit rate for mcbsp-to-mcbsp communications is 100 mhz; therefore, the minimum clkr/x clock cycle is either twice the cpu cycle time (2p), or 10 ns (100 mhz), whichever value is larger. for example, when running parts at 200 mhz (p = 5 ns), use 10 ns as the minimum clkr/x clock cycle (by setting the appropriate clkgdv ratio or external clock source). whe n running parts at 100 mhz (p = 10 ns), use 2p = 20 ns (50 mhz) as the minimum clkr/x clock cycle. the maximum bit rate for mcbsp-to-mcb sp communications applies when the serial port is a master of the clock and frame syncs (with clkr connected to clkx, fsr connecte d to fsx, clkxm = fsxm = 1, and clkrm = fsrm = 0) in data delay 1 or 2 mode (r/xdatdly = 01b or 10b) and the other device the mcbsp communicates to is a slave. ? the minimum clkr/x pulse duration is either (p ? 1) or 4 ns, whichever is larger. for example, when running parts at 200 mhz (p = 5 ns), use 4 ns as the minimum clkr/x pulse duration. when running parts at 100 mhz (p = 10 ns), use (p ? 1) = 9 ns as the minimum clkr/x pulse duration.
sprs106d ? october 1999 ? revised february 2003 51 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) switching characteristics over recommended operating conditions for mcbsp ?? (see figure 31) no parameter ? 200 unit no. parameter min max unit 1 t d(cksh-ckrxh) delay time, clks high to clkr/x high for internal clkr/x generated from clks input 3 12 ns 2 t c(ckrx) cycle time, clkr/x clkr/x int 2p ? 2 ? ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x int c ? 2 # c + 2 # ns 4 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr int ? 3 3 ns 9 t dela time clkx high to internal fsx alid clkx int ? 3 3 ns 9 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx ext 3 9 ns 12 t disable time, dx hi g h impedance followin g last data bit from clkx int ? 1 4 ns 12 t dis(ckxh-dxhz) disable time , dx high im edance following last data bit from clkx high clkx ext 3 9 ns 13 t dela time clkx high to dx alid clkx int ? 1 4 ns 13 t d(ckxh-dxv) delay time, clkx high to dx valid clkx ext 2 12 ns 14 t dela y time, fsx hi g h to dx valid fsx int ? 1 5 ns 14 t d(fxh-dxv) delay time , fsx high to dx valid only applies when in data delay 0 (xdatdly = 00b) mode. fsx ext 2 12 ns ? clkrp = clkxp = fsrp = fsxp = 0. if the polarity of any of the signals is inverted, then the timing references of that signal a re also inverted. ? minimum delay times also represent minimum output hold times. p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? the maximum bit rate for the c6205 devices is 100 mbps or cpu/2 (the slower of the two). care must be taken to ensure that the ac timings specified in this data sheet are met. the maximum bit rate for mcbsp-to-mcbsp communications is 100 mhz; therefore, the minimum clkr/x clock cycle is either twice the cpu cycle time (2p), or 10 ns (100 mhz), whichever value is larger. for example, when running parts at 200 mhz (p = 5 ns), use 10 ns as the minimum clkr/x clock cycle (by setting the appropriate clkgdv ratio or external clock source). whe n running parts at 100 mhz (p = 10 ns), use 2p = 20 ns (50 mhz) as the minimum clkr/x clock cycle. the maximum bit rate for mcbsp-to-mcb sp communications applies when the serial port is a master of the clock and frame syncs (with clkr connected to clkx, fsr connecte d to fsx, clkxm = fsxm = 1, and clkrm = fsrm = 0) in data delay 1 or 2 mode (r/xdatdly = 01b or 10b) and the other device the mcbsp communicates to is a slave. # c = h or l s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero clkgdv should be set appropriately to ensure the mcbsp bit rate does not exceed the 100-mhz limit.
sprs106d ? october 1999 ? revised february 2003 52 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) bit(n-1) (n-2) (n-3) bit 0 bit(n-1) (n-2) (n-3) 14 13 12 11 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 clks clkr fsr (int) fsr (ext) dr clkx fsx (int) fsx (ext) fsx (xdatdly=00b) dx 13 figure 31. mcbsp timings
sprs106d ? october 1999 ? revised february 2003 53 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) timing requirements for fsr when gsync = 1 (see figure 32) no ? 200 unit no. min max unit 1 t su(frh-cksh) setup time, fsr high before clks high 4 ns 2 t h(cksh-frh) hold time, fsr high after clks high 4 ns 2 1 clks fsr external clkr/x (no need to resync) clkr/x (needs resync) figure 32. fsr timing when gsync = 1
sprs106d ? october 1999 ? revised february 2003 54 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 ?? (see figure 33) ? 200 no. master slave unit no. min max min max unit 4 t su(drv-ckxl) setup time, dr valid before clkx low 12 2 ? 3p ns 5 t h(ckxl-drv) hold time, dr valid after clkx low 4 6 + 6p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 ?? (see figure 33) ? 200 no. parameter master slave unit no. parameter min max min max unit 1 t h(ckxl-fxl) hold time, fsx low after clkx low ? t ? 3 t + 5 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high # l ? 4 l + 5 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid ? 4 5 3p + 3 5p + 17 ns 6 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low l ? 2 l + 3 ns 7 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high p + 3 3p + 17 ns 8 t d(fxl-dxv) delay time, fsx low to dx valid 2p + 2 4p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).
sprs106d ? october 1999 ? revised february 2003 55 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr figure 33. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0
sprs106d ? october 1999 ? revised february 2003 56 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 ?? (see figure 34) ? 200 no. master slave unit no. min max min max unit 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 ? 3p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 6p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 ?? (see figure 34) ? 200 no. parameter master slave unit no. parameter min max min max unit 1 t h(ckxl-fxl) hold time, fsx low after clkx low ? l ? 2 l + 3 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high # t ? 2 t + 3 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid ? 2 4 3p + 4 5p + 17 ns 6 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low ? 2 4 3p + 3 5p + 17 ns 7 t d(fxl-dxv) delay time, fsx low to dx valid h ? 2 h + 4 2p + 2 4p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 4 3 7 6 2 1 clkx fsx dx dr 5 figure 34. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0
sprs106d ? october 1999 ? revised february 2003 57 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 ?? (see figure 35) ? 200 no. master slave unit no. min max min max unit 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 ? 3p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 6p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 ?? (see figure 35) ? 200 no. parameter master slave unit no. parameter min max min max unit 1 t h(ckxh-fxl) hold time, fsx low after clkx high ? t ? 2 t + 3 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low # h ? 2 h + 3 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid ? 2 4 3p + 4 5p + 17 ns 6 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high h ? 2 h + 3 ns 7 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high p + 3 3p + 17 ns 8 t d(fxl-dxv) delay time, fsx low to dx valid 2p + 2 4p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).
sprs106d ? october 1999 ? revised february 2003 58 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr figure 35. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1
sprs106d ? october 1999 ? revised february 2003 59 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 ?? (see figure 36) ? 200 no. master slave unit no. min max min max unit 4 t su(drv-ckxl) setup time, dr valid before clkx low 12 2 ? 3p ns 5 t h(ckxl-drv) hold time, dr valid after clkx low 4 5 + 6p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 ?? (see figure 36) ? 200 no. parameter master slave unit no. parameter min max min max unit 1 t h(ckxh-fxl) hold time, fsx low after clkx high ? h ? 2 h + 3 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low # t ? 2 t + 1 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid ? 2 4 3p + 4 5p + 17 ns 6 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high ? 2 4 3p + 3 5p + 17 ns 7 t d(fxl-dxv) delay time, fsx low to dx valid l ? 2 l + 4 2p + 2 4p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 7 6 2 1 clkx fsx dx dr figure 36. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1
sprs106d ? october 1999 ? revised february 2003 60 post office box 1443 ? houston, texas 77251 ? 1443 dmac, timer, power-down timing switching characteristics over recommended operating conditions for dmac outputs ? (see figure 37) no parameter ? 200 unit no. parameter min max unit 1 t w(dmach) pulse duration, dmac high 2p ? 3 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. dmac[3:0] 1 figure 37. dmac timing timing requirements for timer inputs ? (see figure 38) no ? 200 unit no. min max unit 1 t w(tinph) pulse duration, tinp high 2p ns 2 t w(tinpl) pulse duration, tinp low 2p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. switching characteristics over recommended operating conditions for timer outputs ? (see figure 38) no parameter ? 200 unit no. parameter min max unit 3 t w(touth) pulse duration, tout high 2p ? 3 ns 4 t w(toutl) pulse duration, tout low 2p ? 3 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. tinpx toutx 4 3 2 1 figure 38. timer timing
sprs106d ? october 1999 ? revised february 2003 61 post office box 1443 ? houston, texas 77251 ? 1443 dmac, timer, power-down timing (continued) switching characteristics over recommended operating conditions for power-down outputs ? (see figure 39) no parameter ? 200 unit no. parameter min max unit 1 t w(pdh) pulse duration, pd high 2p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 200 mhz, use p = 5 ns. pd 1 figure 39. power-down timing
sprs106d ? october 1999 ? revised february 2003 62 post office box 1443 ? houston, texas 77251 ? 1443 jtag test-port timing timing requirements for jtag test port (see figure 40) no ? 200 unit no. min max unit 1 t c(tck) cycle time, tck 35 ns 3 t su(tdiv-tckh) setup time, tdi/tms/trst valid before tck high 11 ns 4 t h(tckh-tdiv) hold time, tdi/tms/trst valid after tck high 9 ns switching characteristics over recommended operating conditions for jtag test port (see figure 40) no parameter ? 200 unit no. parameter min max unit 2 t d(tckl-tdov) delay time, tck low to tdo valid ? 4.5 12 ns tck tdo tdi/tms/trst 1 2 3 4 2 figure 40. jtag test-port timing
sprs106d ? october 1999 ? revised february 2003 63 post office box 1443 ? houston, texas 77251 ? 1443 mechanical data ghk (s-pbga-n288) plastic ball grid array 1,40 max 0,85 0,08 0,12 0,45 0,55 0,35 0,45 0,95 15,90 sq 16,10 4145273-4/c 12/99 seating plane 7 j b a 1 d c e g f h 24 3 6 5 t k m l p n r w u v 12 8 9 10 11 15 14 13 16 17 14,40 typ 18 19 0,80 0,10 0,80 m ? 0,08 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. microstar bga configuration thermal resistance characteristics (s-pbga package) no c/w air flow (m/s ? ) 1 r jc junction-to-case 9.5 n/a 2 r ja junction-to-free air 26.5 0.00 3 r ja junction-to-free air 23.9 0.50 4 r ja junction-to-free air 22.6 1.00 5 r ja junction-to-free air 21.3 2.00 ? m/s = meters per second microstar bga is a trademark of texas instruments.
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third?party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2003, texas instruments incorporated

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